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' 5 $ 0 $ g y d q f h l q i r u p d w l r q copyright ?1998 alliance semiconductor. all rights reserved. ? $ 6 / & 0 6 $ 6 / & 0 6 ', ',' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 9 0 e 0 e & 0 2 6 v \ q f k u r q r x v ' 5 $ 0 6hohfwlrqjxlgh symbol as4lc2m8s0-8 as4lc2m8s0-10 as4lc2m8s0-12 unit bus frequency (cl = 3) f max 125 100 83.3 mhz maximum clock access time (cl = 3) t ac 678.5ns minimum input setup time t s 223.0ns minimum input hold time t h 1.0 1.0 1.0 ns row cycle time (cl=3, bl=1) t rc 72 80 90 ns maximum operating current i cc1 100 80 75 ma maximum cmos standby current, self refresh i cc6 1 1 1 ma 3lqghvljqdwlrq pin(s) description dqm (2m8) udqm/ldqm (1m16) output disable/write mask a0 to a10 address inputs a11 bank select dq0 to dq7 (2m8) dq0 to dq15 (1m16) input/output ras row address strobe cas column address strobe we write enable cs chip select v cc , v ccq power (3.3v 0.3v) v ss , v ssq ground clk clock input cke clock enable 3lqduudqjhphqw v cc dq0 dq1 v ssq dq2 dq3 v ccq dq4 dq5 v ssq dq6 dq7 v ccq ldqm we v ss dq15 dq14 v ssq dq13 dq12 v ccq dq11 dq10 v ssq dq9 dq8 v ccq nc udqm clk cke nc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 tsop ii as4lc1m16s0 23 24 25 28 27 26 cas ras cs a11 a10 a0 a1 a2 a3 v cc a9 a8 a7 a6 a5 a4 v ss v cc dq0 v ssq dq1 v ccq dq2 v ssq dq3 v ccq nc nc we cas ras cs a11 a10 a0 a1 a2 a3 v cc v ss dq7 v ssq dq6 v ccq dq5 v ssq dq4 v ccq nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 v ss 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 tsop ii a s4lc2m8s0 )hdwxuhv ? organization: 1,048,576 words 8 bits 2 banks (2m8) 524,288 words 16 bits 2 banks (1m16) ? all signals referenced to positive edge of clock ? dual internal banks controlled by a11 (bank select) ? high speed - 125/100/83 mhz - 6/7/8.5 ns clock access time ? low power consumption - active: 576 mw max - standby: 7.2 mw max, cmos i/o ? 4096 refresh cycles, 64 ms refresh interval ? auto refresh and self refresh ? automatic and direct precharge ? burst read, single write ? can assert random column address in every cycle ? lvttl compatible i/o ? 3.3v power supply ? jedec standard package, pinout and function - 400 mil, 44-pin tsop ii (2m8) - 400 mil, 50-pin tsop ii (1m16) ? read/write data masking ? programmable burst length (1/2/4/8/full page) ? programmable burst sequence (sequential/interleaved) ? programmable cas latency (1/2/3)
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ )xqfwlrqdoghvfulswlrq the as4lc2m8s0 and as4lc1m16s0 are high performance 16 megabit cmos synchronous dynamic random access memories (sdram) organized as 1,048,576 words 8 bits 2 banks and 524,288 words 16 bits 2 banks, respectively. very high bandwidth is ach ieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. programmable b urst mode can be used to read up to a full page of data (512 bytes for 2m8 and 256 bytes for 1m16) without selecting a new column addre ss. the two internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving ope rations. this provides a significant advantage over asynchronous edo and fast page mode devices. this sdram product also features a programmable mode register, allowing users to select read latency as well as burst length an d type (sequential or interleaved). lower latency improves first data access in terms of clk cycles, while higher latency improves max imum frequency of operation. this feature enables flexible performance optimization for a variety of applications. dram commands and functions are decoded from control inputs. basic commands are as follows: ? mode register set ? de-activate bank ? deactivate all banks ? select row, activate bank ? select column, write ? select column, read ? deselect, power down ? cbr refresh ? auto precharge with read/write ? self refresh both devices are available in 400 mil plastic tsop type 2 package. the as4lc2m8s0 has 44 pins, and the as4lc1m16s0 has 50 pins. both devices operate with a power supply of 3.3v 0.3v. multiple power and ground pins are provided for low switching noise and emi . inputs and outputs are lvttl compatible. /rjlfeorfngldjudp ? for as4lc1m16s0, banks a & b will read 1m16 (102425616). ras cas we clk cke clock generator mode register command decoder control logic row address buffer refresh counter column address buffer burst counter row decoder sense amplifier column decoder and latch circuit data control circuit latch circuit input and output buffer dq a[10:0] dqm cs bank select a11 bank b ? 1m8 (10245128) bank a ? 1m8 (10245128)
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 5hfrpphqghgrshudwlqjfrqglwlrqv ? v il min = -1.5v for pulse widths less than 5 ns. ? i oh = -2ma, and i ol = 2ma recommended operating conditions apply throughout this document unless otherwise specified. $evroxwhpd[lpxpudwlqjv stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended periods may affect reliability. parameter symbol min nominal max unit supply voltage v cc ,v ccq 3.0 3.3 3.6 v gnd 0.0 0.0 0.0 v input voltage v ih 2.0 C v cc + 0.3 v v il C0.3 ? C0.8v output voltage ? v oh 2.4CCv v ol CC0.4v ambient operating temperature t a 070c parameter symbol min max unit input voltage v in ,v out -1.0 +4.6 v power supply voltage v cc ,v ccq -1.0 +4.6 v storage temperature (plastic) t stg -55 +150 c power dissipation p d C1w short circuit output current i out C50ma
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ '&hohfwulfdofkdudfwhulvwlfv cl = cas latency 1 this parameter depends on output loading and cycle rates. measured with outputs open, inputs only change one time during t ck (min). 2 assumed t ccd (min) 3 refresh period = 64ms. 4 low power version parameter symbol test conditions -8 -10 -12 unit notes min max min max min max input leakage current i il 0v v in v cc , pins not under test = 0v -5 +5 -5 +5 -5 +5 a output leakage current i ol d out disabled, 0v v out v ccq -5 +5 -5 +5 -5 +5 a operating current (one bank active) i cc1 t rc 3 min, iol = 0ma, burst length = 1 C 100 C 80 C 75 ma 1 precharge standby current (power down mode) i cc2p cke v il (max), t ck = 15 ns C2.0C2.0C2.0ma i cc2ps cke & clk v il (max), t ck = C2.0C2.0C2.0ma precharge standby current (non-power-down mode) i cc2n cs 3 v ih (min), cke 3 v ih (min), t cc = 15 ns; input signals changed once during 30 ns C20C20C20ma i cc2ns clk v il (max), cke 3 v ih (min), t ck = ; input signals stable C6C6C6ma active standby current (power down mode) i cc3p cke v il (max), t ck = 15 ns C2C2C2ma i cc3ps clk, cke v il (max), t ck = C2C2C2ma active standby current (non power down mode, one bank active) i cc3n cke 3 v ih (min), cs 3 v ih (min), t ck = 15 ns; input signals changed once during 30 ns C35C27C27ma i cc3ns cke 3 v ih (min), clk 3 v il (max), t ck = ; input signals stable C12C10C10ma operating current (burst mode) i cc4 i ol = 0 ma page burst all banks activated t ccd = t ccd (min) cl =3 C 130 C 120 C 110 ma 1,2 cl =2 C 95 C 85 C 80 cl =1 C 70 C 60 C 55 refresh current i cc5 t rc 3 t rc (min) C 70 C 65 C 65 ma 3 self refresh current icc6 cke 0.2 v C2C2C2ma C1C1C1ma4
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 $&sdudphwhuvfrpprqwrdoozdyhirupv 1 minimum clock cycles = (minimum time / clock cycle time) rounded up 2 minimum delay required to complete write. 3 column address change allowed every cycle. 4 parameters dependent on cas latency. 5 if clock rising time > 1ns, (tr/2-0.5)ns should be added to parameter. 6 if (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter. symbol parameter cas latency -8 -10 -12 unit notes min max min max min max t rrd row active to row active delay 16 C 20 C 24 C ns 1 t rcd ras to cas delay time 20 C 26 C 30 C ns 1 t rp row precharge 20 C 26 C 30 C ns 1 t ras row active 48 100,000 50 100,000 60 100,000 ns 1 t rc row cycle time 72 C 80 C 90 C ns 1 t cdl last data in to new column address delay 1 C 1 C 1 C clk 2 t rdl last data in to row precharge 1 C 1 C 1 C clk 2 t bdl last data in to burst stop 1 C 1 C 1 C clk 2 t ccd column address to column address delay 1 C 1 C 1 C clk 3 t ck clk cycle time 3 8 1000 10 1000 12 1000 ns 4 2 10 1000 14 1000 15 1000 4 1 20 1000 28 1000 30 1000 4 t ac clk to valid output delay 3C6C7C8.5 ns 4,5 2 C 6 C 8.5 C 9.0 4,5 1 C 16 C 23 C 25 4,5 t oh output data hold time 33C3C3C ns 23C3C3C 13C3C3C t ch clk high pulse width 3 C 3.5 C 4 C ns 6 t cl clk low pulse width 3 C 3.5 C 4 C ns 6 t s input setup time 2 C 2 C 3 C ns 6 t h input hold time 1 C 1 C 1 C ns 6 t slz clk to output in low z 1 1 C 1 C 1 C ns 5 t shz clk to output in high z 336C8C8 ns 237C11C11 1 3 15 C 18 C 18
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ 2shudwlqjprghv 1 op = operation code a0~a11 see page 8 2 mrs can be issued only when both banks are precharged. a new command can be issued 2 clock cycles after mrs. 3 auto refresh functions similarly to cbr dram refresh. however, precharge is automatic. auto/self refresh can only be issued after both banks are precharged. 4 a11: bank select address. if low during read, write, row active and precharge, bank a is selected. if high during those states, bank b is selected. both banks are selected and a11 is ignored if a10 is high during row precharge . 5 a new read/write command cannot be issued during a burst read/write with auto precharge. it must be issued after the end of the burst. a new row active command can be issued after t rp from the end of the burst. 6 burst stop command valid at every burst length. 7 dqm sampled at positive edge of clk. data-in may be masked at every clk (write dqm latency is 0). data-out mask is active 2 clk cycles after issuance. (read dqm latency is 2). command cke n-1 cke n cs ras cas we dqm a11 a10 a9Ca0 note mode register set h x l l l l x op code 1,2 auto refresh hhlllhx x 3 self refresh entry h llllhx x 3 exit l h l hhhx x 3 hxxxx x 3 bank activate h x l l h h x v row address read auto precharge disable hxlhlhxv l column address 4 auto precharge enable h 4,5 write auto precharge disable hxlhllxv l column address 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge selected bank hxllhlx vl x both banks xh clock suspend or active power down entry h l hxxxx x lvvvx exit l hxxxxx precharge power down mode entry h l hxxxx x l hhhx exit l h hxxxx lvvvx dqm h xxxxxvxx x 7 no operation command hx hxxxx x l hhhx
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 0rghuhjlvwhuilhogv ? rfu = 0 during mrs cycle. ? burst length = full page when a2~a0 = 1. %xuvwvhtxhqfh exuvwohqjwk register programmed with mrs address a11~a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu ? wbl tm cas latency bt burst length write burst length burst type a9 length a3 type 0 programmed burst length 0 sequential 1 interleaved 1 single burst test mode a8 a7 type 0 0 mode register set 0 1 reserved 1 0 reserved 1 1 reserved cas latency burst length a6 a5 a4 latency a2 a1 a0 bt = 0 bt = 1 0 0 0 reserved 0 0 0 1 1 0011 0 0122 0102 0 1044 0113 0 1188 1 x x reserved 1 x x reserved ? reserved initial address sequential interleave a1 a0 0 0 01230123 0 1 12301032 1 0 23012301 1 1 30123210
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ %xuvwvhtxhqfh exuvwohqjwk 3lqghvfulswlrqv initial address sequential interleave a2 a1 a0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210 pin name description clk system clock all operations synchronized to rising edge of clk. cke clock enable controls clk input. if cke is high, the next clk rising edge is valid. if cke is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. if both banks are idle and cke goes low, the sdram will enter power down mode from the next clock cycle. when in power down mode and cke is low, no input commands will be acknowledged. to exit power down mode, raise cke high before the rising edge of clk. cs chip select enables or disables device operation by masking or enabling all inputs except clk, cke, dqm. a0~a10 address row and column addresses are multiplexed. row address: a0~a10. column address (2m8): a0~a8. column address (1mx16): a0~a7. a11 bank select memory cell array is organized in 2 banks. a11 selects which internal bank will be active. a11 is latched during bank activate, read, write, mode register set, and precharge operations. asserting a11 low selects bank a; a11 high selects bank b. ras row address strobe enables row access and precharge operation. when ras is low, row address is latched at the rising edge of clk. cas column address strobe enables column access. when cas is low, column address is latched at the rising edge of clk. we write enable enables write operation and row precharge operation. when we is low, input data is latched starting from cas . dqm output disable/ write mask controls i/o buffers. when dqm is high, output buffers are disabled during a read operation and input data is masked during a write operation. dqm latency is 2 clocks for read and 0 clocks for write. dq0~dq15 data input/output data inputs/outputs are multiplexed. v dd /v ss power supply/ground power and ground for core logic and input buffers. v ddq /v ssq data output power/ground power and ground for data output buffers.
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 'hylfhrshudwlrq command pin settings description power up the following sequence is recommended prior to normal operation. 1. apply power, start clock, and assert cke and dqm high. all other signals are nop. 2. after power-up, pause for a minimum of 200s. cke/dqm = high; all oth- ers nop. 3. precharge both banks. 4. perform mode register set command to initialize mode register. 5. perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (steps 4 and 5 may be interchanged.) mode register set cs = ras = cas = we = low; a0~a11 = opcode the mode register stores the user selected opcode for the sdram operating modes. the cas latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the mode register set command cycle. the default setting of the mode register is not defined after power-up. therefore, it is recommended that the power-up and mode register set cycle be executed prior to normal sdram operation. refer to the mode register set table and timing for details. device deselect and no operation cs = high the sdram performs a "no operation" (nop) when ras , cas , and we = high. since the nop performs no operation, it may be used as a wait state in performing normal sdram functions. the sdram is deselected when cs is high. cs high disables the command decoder such that ras , cas , we and address inputs are ignored. device deselection is also considered a nop. bank activation cs = ras = low; cas = we = high; a0~a10 = row address; a11 = bank select the sdram is configured with two internal banks. use the bank activate command to select a row in one of the two idle banks. initiate a read or write operation after t rcd (min) from the time of bank activation. burst read cs = cas = a10 = low; ras = we = high; a11 = bank select, a0~a8 = column address; (a9 = dont care for 2m8; a8,a9 = dont care for 1m16) use the burst read command to access a consecutive burst of data from an active row in an active bank. burst read can be initiated on any column address of an active row. the burst length, sequence and latency are determined by the mode register setting. the first output data appears after the cas latency from the read command. the output goes into a high impedance state at the end of the burst (bl = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write burst write cs = cas = we = a10 = low; ras = high; a0~a9 = column address; (a9 = dont care for 2m8; a8,a9 = dont care for 1m16) use the burst write command to write data into the sdram on consecutive clock cycles to adjacent column addresses. the burst length and addressing mode is determined by the mode register opcode. input the initial write address in the same clock cycle as the burst write command. terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. dqm can also be used to mask the input data. dqm operation use dqm to mask input and output data. it disables the output buffers in a read operation and masks input data in a write operation. the output data is invalid 2 clocks after dqm assertion (2 clock latency). input data is masked on the same clock as dqm assertion (0 clock latency). burst stop cs = we = low; ras = cas = high use burst stop to terminate burst operation. this command may be used to terminate all legal burst lengths.
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ bank precharge cs = a10 = ras = we = low; cas = high; a11 = bank select; a0~a9 = dont care the bank precharge command precharges the bank specified by a11. the precharged bank is switched from active to idle state and is ready to be activated again. assert the precharge command after t ras (min) of the bank activate command in the specified bank. the precharge operation requires a time of t rp (min) to complete. precharge all cs = ras = we = low; cas = a10 = high; a11 = bank select; a0~a9 = dont care the precharge all command precharges both banks simultaneously. both banks are switched to the idle state on precharge completion. auto precharge cs = cas = we (write) = low; ras = we (read) = a10 = high; a11 = bank select; a0~a9 = column address; (a9 = dont care for 2m8; a8,a9 = dont care for 1m16) during auto precharge, the sdram adjusts internal timing to satisfy t ras (min) and t rp for the programmed cas latency and burst length. couple the auto precharge with a burst read/write operation by asserting a10 to a high state at the same time the burst read/write commands are issued. at auto precharge completion, the specified bank is switched from active to idle state. note that no new commands can be issued until the specified bank achieves the idle state clock suspend/ power down mode entry cke = low when cke is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. if both banks are idle and cke goes low, the sdram enters power down mode at the next clock cycle. when in power down mode, no input commands are acknowledged as long as cke remains low. to exit power down mode, raise cke high before the rising edge of clk. clock suspend/ power down mode exit cke = high resume internal clock operation by asserting cke high before the rising edge of clk. subsequent commands can be issued one clock cycle after the end of the exit command. auto refresh cs = ras = cas = low; we = cke = high; a0~a11 = dont care sdram storage cells must be refreshed every 64ms to maintain data integrity. use the auto refresh command to accomplish the refreshing of all rows in both banks of the sdram. the row address is provided by an internal counter which increments automatically. auto refresh can only be asserted when both banks are idle and the device is not in the power down mode. the time required to complete the auto refresh operation is t rc (min). use nops in the interim until the auto refresh operation is complete. this is the most common refresh mode. it is typically performed once every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. both banks will be in the idle state after this operation. self refresh cs = ras = cas = cke = low; we = high; a0~a11 = dont care self refresh is another mode for refreshing sdram cells. in this mode, refresh address and timing are provided internally. self refresh entry is allowed only when both banks are idle. the internal clock and all input buffers with the exception of cke are disabled in this mode. exit self refresh by restarting the external clock and then asserting cke high. nops must follow for a time of t rc (min) for the sdram to reach the idle state where normal operation is allowed. if burst auto refresh is used in normal operation, burst 4096 auto refresh cycles immediately after exiting self refresh. command pin settings description
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 0rghuhjlvwhuvhwfrppdqgzdyhirup mrs can be issued only when both banks are idle. 3uhfkdujhzdyhirupv precharge can be asserted after t ras (min). the selected bank will enter the idle state after t rp .. the earliest assertion of the precharge command without losing any burst data is show below. qrupdozulwh%/ qrupdouhdg%/ clk cmd pre mrs act t rp t rsc (min) clk cmd dq we pre d 0 d 1 d 2 d 3 clk cmd dq(cl1) dq(cl2) dq(cl3) read data pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ $xwrsuhfkdujhzdyhirupv a10 controls the selection of auto precharge during the read or write command cycle. zulwhzlwkdxwrsuhfkdujh%/ uhdgzlwkdxwrsuhfkdujh%/ *the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of another activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal. &orfnvxvshqvlrquhdgzdyhirupv %/ clk cmd dq we d 0 d 1 d 2 d 3 auto precharge starts* auto precharge starts* clk cmd dq(cl1) dq(cl2) dq(cl3) read data q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open open q 7 clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 open
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 &orfnvxvshqvlrqzulwhzdyhirupv clk external clk internal cke dqm dq q 1 q 2 q 3 q 4 q 6 q 5 clk external clk internal cke dqm dq d1 d2 d3 dqm mask d5 d6 cke mask clk external clk internal cke dqm dq dqm mask cke mask d1 d2 d3 d5 d6 clk external clk internal cke dqm dq d1 d2 d3 d4 d6 d5
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ 5hdgzulwhlqwhuuxswwlplqj uhdglqwhuuxswhge\uhdg%/ t ccd = cas to cas delay (= 1 clk) zulwhlqwhuuxswhge\zulwh%/ t ccd = cas to cas delay (= 1 clk) t cdl = last address in to new column addres delay (= 1 clk) zulwhlqwhuuxswhge\uhdg%/ t ccd = cas to cas delay (= 1 clk) t cdl = last address in to new column addres delay (= 1 clk) clk cmd add dq (cl1) dq (cl2) dq (cl3) read data read data ab qa 0 qb 0 qb 1 qb 2 qb 3 qa 0 qb 0 qb 1 qb 2 qb 3 qa 0 qb 0 qb 1 qb 2 qb 3 t ccd clk cmd add dq da 0 db 0 db 1 db 2 db 3 a 0 b 0 write data write data t ccd t cdl t cdl clk cmd add dq (cl1) dq (cl2) dq (cl3) write data read data ab da 0 qb 0 qb 1 qb 2 qb 3 da 0 qb 0 qb 1 qb 2 qb 3 da 0 qb 0 qb 1 qb 2 qb 3 t ccd
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 uhdglqwhuuxswhge\zulwh&/ %/ to prevent bus contention, maintain a gap between data in and data out. uhdglqwhuuxswhge\zulwh&/ %/ to prevent bus contention, maintain a gap between data in and data out. clk cmd1 dqm1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 read data write data d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 read data write data read data write data q 1 q 0 clk cmd1 dqm1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 cmd4 dqm4 dq4 read data write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 read data write data d 0 d 1 d 2 d 3 q 0
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ uhdglqwhuuxswhge\zulwh&/ %/ to prevent bus contention, maintain a gap between data in and data out. %xuvwwhuplqdwlrq burst operations may be terminated with a read, write, burst stop, or precharge command. when burst stop is asserted during the read cycle, burst read data is terminated and the data bus goes to hi-z after cas latency. when burst stop is asserted during the write cycle, burst write data is terminated and the databus goes to hi-z simultaneously. %xuvwvwrsfrppdqgzdyhirup uhdgf\foh zulwhf\foh%/ clk cmd1 dq1 cmd2 dqm2 dq2 cmd3 dqm3 dq3 cmd4 dqm4 dq4 read data write data read data write data read data write data read data write data d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 dqm1 clk cmd dq (cl = 1) dq (cl = 2) dq (cl = 3) read data burst stop read data q 0 q 1 q 2 q 0 q 1 q 2 q 0 q 1 q 2 clk cmd dq burst stop write data (cl = 1,2,3) dq d 1 d 2 d 3
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 3uhfkdujhwhuplqdwlrq a precharge command terminates a burst read/write operation during the read cycle. the same bank can be activated after meeting t rp . uhdgf\foh&/ uhdgf\foh&/ uhdgf\foh&/ zulwhf\foh clk cmd dq read data pre act q 0 q 1 q 2 q 3 t rp clk cmd dq read data pre act q 0 q 1 q 2 q 3 clk cmd dq read data pre act q 0 q 1 q 2 t rp q 3 clk cmd dq write data pre act d 0 d 1 d 2 d 3 q 4 t rp
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ $xwruhiuhvkzdyhirup 6hoiuhiuhvkzdyhirup clk cs ras cas we a10 a0-a9 dqm cke dq t rp t rc t rc auto refresh precharge both banks auto refresh auto refresh clk cs ras cas we a11 a0-a10 dqm cke dq precharge both banks t rc self refresh entry self refresh exit self refresh cycle arbitrary cycle
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 3rzhugrzqprghzdyhirup &/ enter power down mode by pulling cke low. all input/output buffers (except cke buffer) are turned off in power down mode. when cke goes high, command input must be equal to no operation at next clk rising edge. 5hdgzulwhzdyhirup %/ &/ power down mode active standby clk cs ras cas we a11 a10 a0-a9 dqm cke dq ra a ra a ca a ca x ra a ra a bank activate power down mode entry power down mode exit nop power down mode entry power down mode precharge standby nop power down mode exit bank activate a b0 ra a clk cs ras cas we a11 a10 a0-a9 dqm cke dq ca a ra a ca b ra b ra b t ras t rcd a a0 a a5 a a4 a a3 a a2 a a1 a b5 a b4 a b3 a b2 a b1 bank activate read q qqq q q d ddd d d bank activate write precharge t rp
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ %xuvwuhdgvlqjohzulwhzdyhirup %/ &/ ,qwhuohdyhgedqnuhdgzdyhirup %/ &/ single clk cs ras cas we a11 a10 a9 dqm cke dq ra a ca a ra a ca b ca c ca d activate read read write a a0 a a5 a a4 a a3 a a2 a a1 a d0 a d3 a d2 a d1 q q q q q q q q d d clk cs ras cas we a11 a10 a0-a9 dqm cke dq t ccd t ccd t ccd t ras t rcd t rcd ra a rb a ca a ca b cb b ca c qa a0 qa a3 qa a2 qa a1 qb a0 qa b1 qa b0 qb a1 qa b2 qa c2 qa c1 qa c0 qb b0 qb b3 qb b2 qb b1 bank a: bank b: active read read read read precharge ra a cb a precharge rb a read
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ,qwhuohdyhgedqnuhdgzdyhirup %/ &/ $xwrsuhfkdujh ap = internal precharge begins clk cs ras cas we a11 a10 a9 dqm cke dq t rc t rc t rc t ras t rp t ras t rp t ras t ras t rp t ras t rcd t rcd t rcd t rcd qa a0 qa a2 qa a1 qb b3 qb b2 qb b1 qa a0 qa a1 qb b0 ra a ra a ra b ra b ca a cb b cb c cb d ra c ra d ra e ra c ra d ra e t rrd t rrd t rrd t rrd bank a: bank b: active read active ap active read ap read active active ap read qa a2 qa a3 qb b0 qa a3
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ ,qwhuohdyhgedqnuhdgzdyhirup %/ &/ ,qwhuohdyhgedqnuhdgzdyhirup %/ &/ $xwrsuhfkdujh ap = internal precharge begins clk cs ras cas we a11 a10 a9 dqm cke dq t rc t rc t rc t ras t ras t ras t rp t rp t rp t rcd t rcd t rcd ra a ra a ca a rb b rb b cb b ra c ra c ca c qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qb b4 qb b5 qb b6 qb b7 qa c0 qa c1 bank a: bank b: active read precharge read precharge active precharge active read clk cs ras cas we a11 a10 a9 dqm cke dq qa a0 qa a1 qa a2 qa a3 qa a4 qa a5 qa a6 qb b0 qb b1 qa a7 t rc t rc t ras t ras t rp t ras t rp t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c qb b4 qb b5 qb b6 qa c0 qa c0 t rrd t rrd active read active read bank a bank b ap active read ap
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ,qwhuohdyhgedqnzulwhzdyhirup %/ ,qwhuohdyhgedqnzulwh %/ $xwrsuhfkdujh ap = internal precharge begins clk cs ras cas we a11 a10 a9 dqm cke dq t rc t ras t rp t ras t rp t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b1 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c1 da c2 active write active write bank a bank b active write precharge precharge clk cs ras cas we a11 a10 a9 dqm cke dq active write active write bank a bank b active write ap bank a ap bank b t rc t ras t rp t ras t ras t rcd t rcd t rcd ca a ra a rb b rb b ca b ca c ra a ra c ra c da a0 da a1 da a4 da a5 da a6 da a7 db b0 db b1 db b2 db b3 db b4 db b5 db b6 db b7 da c0 da c1 da c2
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ 3dfndjhglphqvlrqv $&whvwfrqglwlrqv &dsdflwdqfh 15 | 0+]7 d ?&9 && 9 2ughulqjlqirupdwlrq parameter symbol signals max unit input capacitance c in1 a0 to a11 4 pf c in2 dqm, ras , cas , we , cs , clk, cke, 4 pf i/o capacitance c i/o dq0 to dq7 (2m8) dq0 to dq15 (1m16) 5pf package \1/ frequency 8 ns 10 ns 12 ns tsop ii, 400 mil, 44-pin as4lc2m8s0-8tc as4lc2m8s0-10tc AS4LC2M8S0-12TC tsop ii, 400 mil, 50-pin as4lc1m16s0-8tc as4lc1m16s0-10tc as4lc1m16s0-12tc 44-pin tsop ii 50-pin tsop ii min (mm) max (mm) min (mm) max (mm) aC1.2 1.2 a 1 0.05 C 0.05 a 2 0.95 1.05 0.95 1.05 b 0.30 0.45 0.30 0.45 c 0.127 (typical) 0.12 0.21 d 18.28 18.54 20.85 21.05 e 10.03 10.29 10.03 10.29 h e 11.56 11.96 11.56 11.96 e 0.80 (typical) 0.80 (typical) l 0.40 0.60 0.40 0.60 d h e 1234567891011121314 50 49 48 47 46 45 44 43 42 41 40 39 38 37 15 16 36 35 17 18 19 20 34 33 32 31 c l a 1 a 2 e tsop ii 0C5 21 30 22 23 24 25 29 28 27 26 e a b - input reference levels of v ih = 2.4v and v il = 0.4v - output reference levels = 1.4v - input rise and fall times: 2 ns c load = 50 pf d out +1.4v figure a: equivalent output load 50 w z 0 = 50 w
' 5 $ 0 ? $ 6 / & 0 6 $ 6 / & 0 6 $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 3duwqxpehulqjv\vwhp as4 lc xxxs0 Cxx t c dram prefix lc = 3.3v cmos device number for synchronous dram 1/frequency package (device dependent): tsop ii 400 mil, 44 pin tsop ii 400 mil, 50 pin commercial temperature range, 0c to 70 c
' 5 $ 0 $ 6 / & 0 6 $ 6 / & 0 6 ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $

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